The USRP-2974 is ideal for prototyping a range of advanced research applications that include stand-alone LTE or 802.11 device emulation; Medium Access Control (MAC) algorithm development; multiple input, multiple output (MIMO) systems; heterogeneous networks; LTE relaying; RF compressive sampling; spectrum sensing; cognitive radio; beamforming; and direction finding.

• Stand-alone (embedded) or host-based (network streaming) operation
• LabVIEW Communications System Design Suite support for programming both the FPGA and the host, with NI Linux Real-Time.
• LabVIEW Communications 802.11 Application Framework to provide a modifiable FPGA-based 802.11 MAC and PHY reference design
• LabVIEW Communications LTE Application Framework to provide a modifiable FPGA-based LTE MAC and PHY reference design

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This stand-alone SDR features a 2×2 MIMO transceiver providing up to 56 MHz of bandwidth spanning frequencies from 70 MHz to 6 GHz to cover multiple bands of interest. The baseband processor uses the Xilinx Zynq-7020 System-on-Chip to deliver FPGA accelerated computations combined with stand-alone operation enabled by a dual-core ARM CPU.

The USRP Embedded Series platform uses the OpenEmbedded framework to create custom Linux distributions tailored to application specific needs. To reduce development effort the default operating system supports the USRP Hardware Driver™ (UHD) software API, as well as a variety of third party tools such as GNU Radio. Support for the RF Network on Chip (RFNoC™) FPGA development framework enables deterministic computations for real-time and wideband signal processing. Users can rapidly prototype and reliably deploy designs for embedded applications intended for the unpredictable outdoors.

Table 1: Operating system and development frameworks

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The baseband processor uses the Xilinx Zynq 7020 SoC to deliver FPGA accelerated computations combined with stand-alone operation enabled by a dual-core ARM CPU. The USRP E310 includes a rich set of peripherals such as an integrated GPS receiver for position awareness and time synchronization, as well as two host USB ports for extending storage, I/O, and communication options with off-the-shelf devices. Users can rapidly prototype and deploy designs for mobile and embedded applications with tight size, weight, and power requirements.

The USRP Embedded Series platform uses the OpenEmbedded framework to create custom Linux distributions tailored to application specific needs. The default operating system is pre-installed with the UHD software API and a variety of third party development tools such as GNU Radio. Support for the RFNoC FPGA development framework enables deterministic computations for real-time and wideband signal processing.

Table 1: Operating system and development frameworks

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E310 first appeared on EgeRate Elektronik.

The baseband processor uses the Xilinx Zynq 7020 SoC to deliver FPGA accelerated computations combined with stand-alone operation enabled by a dual-core ARM CPU. The USRP E312 includes a rich set of peripherals such as an integrated GPS receiver for position awareness and time synchronization, as well as two host USB ports for extending storage, I/O, and communication options with off-the-shelf devices. Users can rapidly prototype and deploy designs for mobile and embedded applications with tight size, weight, and power requirements.

The USRP Embedded Series platform uses the OpenEmbedded framework to create custom Linux distributions tailored to application specific needs. The default operating system is pre-installed with the UHD software API and a variety of third party development tools such as GNU Radio. Support for the RFNoC FPGA development framework enables deterministic computations for real-time and wideband signal processing.

Table 1: Operating system and development frameworks

Filter Banks

The USRP E312 contains both RX and TX filter banks. Filters are dynamically chosen based on user frequency selection. The RX filters reduce interference from out-of-band signals, while the TX filters suppress harmonics.

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The USRP E320 is available in both 3U board-only and fully enclosed form factor variants. The compact size of the USRP E320 is highly suitable for deployment as a mobile radio in manpacks or mounted on unmanned ariel vehicles.

The open-source USRP Hardware Driver (UHD) API and RF Network-on-Chip (RFNoC) FPGA development framework reduce software development effort and integrate with a variety of industry-standard tools such as GNU Radio. Users can rapidly prototype and reliably deploy designs for a variety of SDR applications such as spectrum monitoring and analysis, base station and UE emulation, mobile radio, and UAV communication/detection.

Baseband Processor
The baseband processor uses the Xilinx Zynq-7045 SoC to deliver a large user-programmable FPGA for real-time and low-latency processing and a dual-core ARM CPU for stand-alone operation. Users can deploy applications directly on to the preinstalled embedded Linux operating system or stream samples to a host computer using high-speed interfaces such as 1 Gigabit Ethernet, 10 Gigabit Ethernet, and Aurora.

Synchronization
The USRP E320 has a flexible synchronization architecture with support for traditional SDR synchronization methods such as clock reference, PPS time reference, and GPSDO, which enable implementation of high channel count MIMO systems.

Trusted Platform Module (TPM)
The USRP E320 includes a Trusted Platform Module to enable security features such as file encryption. Due to product compliance restrictions on products with TPM (Trusted Platform Module) components to a few countries, the USRP E320 is available in two variants:

• Standard variant with TPM (PN 786189-01)
• Non-TPM variant (PN 786878-01)

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Table 1: Operating systems, development frameworks, and reference applications

High-Performance User-Programmable FPGA

At the heart of the USRP X300, the XC7K325T FPGA provides high-speed connectivity between all major components within the device including radio frontends, host interfaces, and DDR3 memory. The default FPGA core provided with UHD provides all of the functional blocks for digital down-conversion and up-conversion, fine-frequency tuning, and other DSP functions allowing it to be interchangeable with other USRP devices using the UHD architecture. The large Kintex-7 FPGA provides additional space for developers to incorporate custom DSP blocks and is compatible with a large number of USRP-supported development frameworks, reference architectures, and open source projects.

Table 2: FPGA resource comparison

Multiple High-Speed Interface Options

The USRP X300 provides multiple interface options. Out of the box, 1 GigE provides a convenient way to get started. For extended bandwidth and lower latency applications such as PHY/MAC research, PCIe x4 provides an efficient bus for deterministic operation. Applications using network recorders or multiple processing nodes can be best served by the 10 GigE interface option.

Additional Features- GPSDO, GPIO, 1 GB DDR3, Synchronization

The X300 includes many additional features that facilitate wireless system development. On-board 1GB DDR3 with flexible access through the FPGA reference design supplements the FPGA resources with buffering and data storage memory. An optional internal GPSDO provides a high-accuracy frequency reference, and global timing alignment to within 50 ns when synchronized to the GPS system. The external GPIO connector allows users to control external components such as amplifiers and switches, accept inputs like event triggers, and observe debug signals. The USRP X300 also includes an internal JTAG adapter that allows FPGA developers to easily load and debug new FPGA images.

*USRP X300 RF daughterboards sold separately
Compatible RF Daughterboards: UBX, CBX, WBX, SBX, LFRX, LFTX, Basic TX/RX)

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Table 1: Operating systems, development frameworks, and reference applications

High-Performance User-Programmable FPGA

At the heart of the USRP X310, the XC7K410T FPGA provides high-speed connectivity between all major components within the device including radio frontends, host interfaces, and DDR3 memory. The default FPGA core provided with UHD provides all of the functional blocks for digital down-conversion and up-conversion, fine-frequency tuning, and other DSP functions allowing it to be interchangeable with other USRP devices using the UHD architecture. The large Kintex-7 FPGA provides additional space for developers to incorporate custom DSP blocks and is compatible with a large number of USRP supported development frameworks, reference architectures, and open source projects.

Table 2: FPGA resource comparison

Multiple High-Speed Interface Options

The USRP X310 provides multiple interface options. Out of the box, 1 GigE provides a convenient way to get started. For extended bandwidth and lower latency applications such as PHY/MAC research, PCIe x4 provides an efficient bus for deterministic operation. Applications using network recorders or multiple processing nodes can be best served by the 10 GigE interface option.

Additional Features- GPSDO, GPIO, 1 GB DDR3, Synchronization

The X310 includes many additional features that facilitate wireless system development. On-board 1GB DDR3 with flexible access through the FPGA reference design supplements the FPGA resources with buffering and data storage memory. An optional internal GPSDO provides a high-accuracy frequency reference, and global timing alignment to within 50 ns when synchronized to the GPS system. The external GPIO connector allows users to control external components such as amplifiers and switches, accept inputs like event triggers, and observe debug signals. The USRP X310 also includes an internal JTAG adapter that allows FPGA developers to easily load and debug new FPGA images.

*USRP X310 RF daughterboards sold separately
Compatible RF Daughterboards: UBX, CBX, WBX, SBX, LFRX, LFTX, Basic TX/RX)

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